1. Field of the Invention
The present invention relates to a non-volatile memory cell and method of operating the same, and more specifically, to a non-volatile memory cell having two transistors and a method of writing, erasing, and reading the same.
2. Description of the Prior Art
Non-volatile memory can store data even without a power supply, and so it is widely used in various portable electronic products such as personal digital assistants (PDAs), mobile phones, and memory cards. In order to respond to these requirements, non-volatile memory technology aims for compatibility with CMOS processing, low power consumption, high writing efficiency, low cost, and high density. However, as non-volatile memory becomes smaller in size, its gate oxide layer becomes accordingly thinner so that stored data vanishes easily, which causes a problem in the data storing ability of non-volatile memory.
Please refer to FIG. 1 showing a conventional memory cell 10. The memory cell 10 includes an N-channel metal oxide semiconductor (NMOS) transistor 28 and a P-channel metal oxide semiconductor (PMOS) transistor 30 separated by an insulating field oxide layer (FOX) 24. The NMOS transistor 28 is formed on a P-type substrate 12 and includes a first floating gate 32, an N+ source doped region 14, and an N+ drain doped region 16. The PMOS transistor 30 is formed on an N-type substrate 18 and includes a second floating gate 34, a P+ source doped region 20, and a P+ drain doped region 22. The PMOS transistor 30 is implanted with a heavily doped N-type channel stop region 38 under the second floating gate 34, adjacent to the P+ source doped region 20. The first floating gate 32 and the second floating gate 34 are connected with a floating gate conductive line 36 so that both are kept at the same level. When writing data into the memory cell 10, the first floating gate 32 generates a corresponding level according to a control gate voltage. At this time, the second floating gate 34 has the same level as the first floating gate 32 because of the connection by the floating gate conductive line 36. Then, the electrons in a depletion region between the P+ source doped region 20 and the N-type channel stop region 38 are accelerated and injected into the second floating gate 34.
However, the conventional memory cell 10 has disadvantages as follows. First, the conventional memory cell 10 comprises the PMOS transistor 30 and the NMOS transistor 28 which occupy a large amount of chip area. Second, the conventional memory cell 10 requires the floating gate conductive line 36 for connecting the first floating gate 32 and the second floating gate 34. Moreover, the field oxide layer 24 is required to separate the PMOS transistor 30 from the NMOS transistor 28. Therefore, the conventional memory cell 10 occupies considerable chip area and is structurally complicated, all of which increase the cost and difficulties in the manufacturing process.